Bookcover of High-Speed CMOS Transceiver
Booktitle:

High-Speed CMOS Transceiver

Principles, Design and Implementation using Multi-level (4-PAM) Signaling

LAP LAMBERT Academic Publishing (2012-09-20 )

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ISBN-13:

978-3-659-21431-8

ISBN-10:
3659214310
EAN:
9783659214318
Book language:
English
Blurb/Shorttext:
With the exponential growth in speed and integration levels of integrated circuits (ICs), the inter-connection bandwidth between chips is becoming the major performance-limiting factor with modern digital systems. High-speed links in the Gbps ranges have been traditionally implemented in GaAs or bipolar technologies. However, CMOS, despite its slower device speed, is now becoming the target technology of choice for high-speed integrated systems due to its widespread availability and higher integration levels possible. This book explores various signaling techniques and circuit architectures for designing a low-cost high-speed serial link in CMOS technology with the objective of maximizing the operating bandwidth and transmission distance. The book provides a thorough overview of the principles, challenges and concepts involved in high-speed transceiver design and describes how to implement a transceiver in CMOS with detailed circuit schematics and simulation results. The book is a valuable resource to any professional or student involved in high-speed circuit design or anyone trying to learn about CMOS transceivers.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
By (author) :
Balu Joseph
Number of pages:
144
Published at:
2012-09-20
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
59.00 €
Keywords:
pll, Data Recovery, CMOS Transceiver, High-Speed Transceiver, Serializer, Deserializer, PAM Signaling, Equalization.

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