Couverture de Implementation of Floating Point Multiplier on Reconfigurable Hardware
Titre du livre:

Implementation of Floating Point Multiplier on Reconfigurable Hardware

Floating Point Multiplier

LAP LAMBERT Academic Publishing (23-01-2013 )

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ISBN-13:

978-3-659-21452-3

ISBN-10:
3659214523
EAN:
9783659214523
Langue du livre:
Anglais
texte du rabat:
Foating point operations are hard to implement on reconfigurable devices because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations. Therefore VHDL programming for IEEE single precision floating point multiplier module have been explored. Various parameters i.e. combinational delay (Latency), chip area (number of slices used), modeling formats, memory usage etc have been analyzed while implementing the floating point multiplier on reconfigurable hardware. Analyzing the various parameters will provide with the information that Vertex4 will consume less chip Area i.e. 663 with reduced latency i.e. 49.906 ns as compared with the other FPGAs i.e. Spartan 2, Spartan 2E, Spartan 3, Spartan 3E, Virtex, Virtex 2, Virtex 2P, and Virtex E. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed.
Maison d'édition:
LAP LAMBERT Academic Publishing
Site Web:
https://www.lap-publishing.com/
de (auteur) :
Karan Gumber
Numéro de pages:
104
Publié le:
23-01-2013
Stock:
Disponible
Catégorie:
Autres
Prix:
49.00 €
Mots-clés:
Xilinx, FPGAs, Floating point adder, Model Sim

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