Portada del libro de CMOS Low Power Analysis
Título del libro:

CMOS Low Power Analysis

Scaling effect & Power Delay Analysis

LAP LAMBERT Academic Publishing (2011-06-01 )

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ISBN-13:

978-3-8443-8277-8

ISBN-10:
3844382771
EAN:
9783844382778
Idioma del libro:
Inglés
Notas y citas / Texto breve:
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.
Editorial:
LAP LAMBERT Academic Publishing
Sitio web:
https://www.lap-publishing.com/
Por (autor):
Vijay Sharma
Número de páginas:
100
Publicado en:
2011-06-01
Stock:
Disponible
Categoría:
Ingeniería mecánica, tecnología de fabricación
Precio:
49.00 €
Palabras clave:
Low Power VLSI, delay, CMOS, Technology Scaling

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