Buchcover von SystemVerilog
Buchtitel:

SystemVerilog

Semiconductor, Hardware description language, Hardware verification language

SpellPress (14.08.2013 )

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ISBN-13:

978-620-1-55219-7

ISBN-10:
6201552197
EAN:
9786201552197
Buchsprache:
Englisch
Klappentext:
Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. SystemVerilog started with the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog standard, creating IEEE Standard 1800-2009, the current version. Verilog-1995 and -2001 limit reg variables to behavioral statements such as RTL code. SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module.
Verlag:
SpellPress
Webseite:
http://www.betascript-publishing.com
Herausgegeben von:
Richie Krishna Fergus
Seitenanzahl:
80
Veröffentlicht am:
14.08.2013
Lagerbestand:
Lieferbar
Kategorie:
Elektronik, Elektrotechnik, Nachrichtentechnik
Preis:
34,00 €
Stichworte:
language, design, SEMICONDUCTOR, Hardware, electronic, Extensions

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