CMOS Low Power Analysis的封面
书籍主题:

CMOS Low Power Analysis

Scaling effect & Power Delay Analysis

LAP LAMBERT Academic Publishing (2011-06-01 )

Books loader

Omni badge 有获得代金券的资格
ISBN-13:

978-3-8443-8277-8

ISBN-10:
3844382771
EAN:
9783844382778
书籍语言:
英文
作品简介:
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.
出版社 :
LAP LAMBERT Academic Publishing
网址:
https://www.lap-publishing.com/
由(作者):
Vijay Sharma
页码 :
100
发表日期:
2011-06-01
现货:
备有现货
类别:
机械工程学,制造技术
价格:
57.82 $
关键词:
Low Power VLSI, delay, CMOS, Technology Scaling

Books loader

时事通讯

Adyen::mc Adyen::visa Adyen::cup Adyen::unionpay Paypal CryptoWallet 银行转帐

LOGIN
  0产品在购物车内
编辑购物车
Loading frontend
LOADING